Application of the Junction Photovoltage (JPV) method for metrology of ultra‐shallow implant (USJ) has been well documented. In this paper we report the application of the JPV method to control implant processes which create an electrically active layer isolated from the surface. In such structures four point probe (4PP) metrology is unreliable or impossible. This paper presents results obtained using a Junction Photo‐Voltage (JPV) method optimized for characterization of these two processes, CMOS: Implantation through a screen oxide followed by anneal and also MeV p‐type high energy implantation into n‐type doped substrate followed by an anneal. Taking errors and necessary corrections into account the JPV method allows accurate high resolution mapping of such structures without the need for an extra process step. Results obtained from the JPV measurements were correlated to destructive off‐line analytical measurement tools.
